This invention relates to digital signal processing systems to enable the digital processing of voice, sonar, radar, video, communication and other analog signals, and more particularly to such a system and architecture to enable the processing of voice analog signals for purposes of narrowband, secure communication and for voice recognition.
The field of digital signal processing is complicated and many patents exist which attempt to process analog voice signals to permit bandwidth reduction to enable digitized, encrypted representation of the analog voice signal to be sent over conventional telephone lines. The same algorithms, such as linear predictive coding, can be used as the front-end processing which extracts features from the analog voice which can then be used in a voice recognition system.
Typical of certain prior art approaches is U.S. Pat. No. 4,070,709 entitled "PIECEWISE LINEAR PREDICTIVE CODING SYSTEM" issued on Jan. 24, 1978 to J. E. Roberts, et al. This patent describes a linear predictive coding (LPC) system that utilizes multichannel signal processing and reduced sampling rates. The input analog signal is divided by filters into multiple, continguous, substantially equal bandwidth signal components and each component is digitized and processed by a separate standard LPC transmit receive system.
Linear predictive coding (LPC) is used to model the vocal tract with a multisection all pole filter to synthesize the voice on the receiving end. The filter coefficients are derived by analyzing the voice at the transmitter by one of several techniques: the covariance method, the autocorrelation method, the lattice method and others. All of these techniques require arithmetic-intensive programs to run in real time. In the covariance method a 10.times.10 covariance matrix is generated and the filter coefficients are derived by inverting the matrix by Cholesky decomposition. In addition to the filter coefficients the pitch period of the speech is derived by, typically, autocorrelation of the digitized voice samples, or by an absolute magnitude difference function AMDF.
In digital signal processing architectures presently implemented, the various functions have required multiple, interconnected integrated circuits. The program, or control, memory, data memory, arithmetic logic unit, multiplier, I/0 circuitry, and timing and control have required one or more integrated circuits for implementation. As fabrication technology has improved, higher density packaging capability has allowed more circuit elements to be integrated in a single integrated circuit chip. Until recently, this has been done by developing more capability within the major types of devices. In memory devices, this has taken the course of more storage capability. In arithmetic elements, this has taken the course of allowing more bits to be processed in parallel. Recently, there is some development in the direction of incorporating more of these basic functions onto one chip. However, in devices that are currently in development which are integrating the various functions onto a single chip the program memory is implemented in ROM. This requires multiple devices in applications where the total program cannot be fitted into the available ROM, which also requires additional external devices to provide the means of connecting several processing elements.
In the current state of the art in semiconductor fabrication, the limitations in implementing the voice algorithms are in limitations of on chip memory capacity rather than processing speed.
The present invention relates to an improved processor which processor can be dynamically programmed by external means in a simple and rapid manner.
The dynamically programmable processor element can be reprogrammed in real time, by a host processor or by accessing local external memory using circuits and an on-board load program. In a stand-alone configuration where there are no other processor elements, the element can also execute instructions by fetching them from external memory. This option is useful where the length of the instruction sequence is shorter than the time required to load the sequence into internal program memory where execution is faster.